Sharad Malik

George Van Ness Lothrop Professor of Engineering and
Professor of Electrical Engineering
Ph.D. 1990, University of California, Berkeley

My research is in electronic design automation (EDA) (also referred to as computer-aided design of electronic systems). The primary objective is to enable electronic system designers to exploit the capabilities provided by semiconductor processing.

The success of the semiconductor industry is in large part due to significant breakthrough contributions in EDA, without which it would not have been possible to harness the rapidly growing semiconductor capabilities. This growth in capabilities has posed a fast-moving target for EDA, with each semiconductor generation posing a new set of challenges. These challenges are more critical today than ever before, with a significant gap between the annual growth rate of semiconductor processing and designer productivity.

One of the primary problems is dealing with system complexity, resulting from the large number of transistors available per integrated circuit (IC or chip). Increasingly, this growth in the number of transistors is being utilized in the form of systems-on-a-chip, where one or more processors are integrated with memory, specialized logic and interface circuitry to form complete single-chip systems. A significant part of the design of such systems is the software component that runs on the processors. This part of the design, referred to as embedded software, is significantly different from traditional software running on desktop and mainframe computers. It typically has harder constraints (size, speed, power) and much smaller size, making it amenable to aggressive analysis and optimization algorithms. I have several research projects directed towards establishing an infrastructure for the analysis and optimization of embedded software. Specifically, we are examining the development of application-specific programmable solutions using a design exploration environment for experimenting with processor and interconnection network architectures. A key element of this infrastructure is retargetable software synthesis and simulation tools that use machine descriptions for synthesizing a processor specific software development environment. This work is part of the MESCAL project (jointly with U.C. Berkeley) of the Gigascale Silicon Research Center.

My interest in the verification of complex systems focuses on the Boolean Satisfiability problem. This problem is at the core of all verification tasks. As part of this research we have developed the Chaff SAT solver, which is used widely in research and industry.

Funding for this research comes from the DARPA-MARCO Gigascale Systems Research Center, the National Science Foundation, the New Jersey Commission on Science and Technology through the Centers for Multimedia Research and Systems-on-a-Chip, Agere Systems, NEC USA and Fujitsu Labs of America.