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Niraj K. Jha

Prof. Jha joined the Department of Electrical Engineering at Princeton University as an assistant professor in 1987, became associate professor in 1993, and full professor in 1998. His research interests include low power hardware and software synthesis, embedded system analysis and design, design algorithms and tools for nanotechnologies, multiprocessor system-on-chip (MPSoC) synthesis, security, digital system testing and quantum computing.

His current research projects are in the areas of low power application and system software, design automation for nanotechnologies and quantum computing, application-specific instruction set processor (ASIP) synthesis, distributed logic-memory architectures, low power interconnection networks, embedded system security and microprocessor testing.

Power consumption has become one of the most important metrics in evaluating a circuit today. This is due to a variety of requirements, such as prolonging battery lifetime in portable devices, reducing chip packaging and cooling costs, and increasing reliability, as well as due to environmental considerations. Prof. Jha's group has produced various low power high-level synthesis and system synthesis tools that are being commercialized. Currently, his focus in this area is on power analysis and optimization tools for both application software and embedded operating systems, as well as energy characterization and optimization of interfaces for handheld computers. He is also collaborating with Prof. Peh to explore thermal issues in MPSoCs.

Nanotechnologies, such as quantum cellular automata (QCA), resonant-tunneling devices (RTDs), single electron transistors (SETs), carbon nanotube transistors, tunneling phase logic, etc., have seen significant advances in the last few years. However, while working devices and logic gates have been demonstrated, development of comprehensive design and analysis methodologies for these technologies are in their infancy. Prof. Jha's group has developed some CAD tools for these technologies and continues to explore this rich area.

Quantum computing has generated a lot of excitement lately. His group is also developing logic synthesis methodologies/tools for reversible logic that is required for quantum computing. Reversible logic also finds applications in nanotechnology, low power design, and optical computing.

Efficiency and flexibility are two major requirements driving embedded system design. Unfortunately, these two requirements are typically at conflict with each other - performance and energy efficiency are often obtained by hardwiring functionality and optimizing the system in an application-specific manner, which limits flexibility, while flexibility is obtained through configurability and/or programmability, which carry associated overheads. ASIPs offer a good tradeoff between efficiency and flexibility by realizing only the critical operations in the application(s) of interest using custom hardware. The recent evolution of customizable and extensible processor technology has provided embedded system designers with a mechanism to design ASIPs with rapid turnaround times through the use of re-targetable software development tool flows, and configurable soft intellectual property (IP). However, the task of customizing the processor and extending it with custom hardware (instruction units, co-processors, peripherals) are still largely manual and left to the designer's expertise. Prof. Jha's group is developing high-level methodologies to tackle this problem.

His group is also working on a high-level synthesis (HLS) approach to high-performance and low-energy distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a controller/datapath communicating with a monolithic memory, or at best a banked or hierarchical memory organization. His group is developing techniques to extend the synthesis frontier to more general architectures that can extract both coarse- and fine-grained parallelism jointly from data accesses and computations.

Security is emerging as an important concern in the embedded system area. Security of embedded systems is often compromised due to vulnerabilities in the ``trusted" software they execute. Security attacks exploit these vulnerabilities. Prof. Jha's group has been working on a hardware-assisted paradigm to enhance embedded system security by detecting and preventing unintended program behavior. He is also collaborating with Prof. Lee on developing energy-efficient architectures to implement security protocols.

In testing, his group is developing SAT-based algorithms and tools to test controller-datapaths of processors, DSPs, ASIPs or ASICs at the register-transfer level, and to use them for low-overhead design for testability. This promises to speed up test generation by two orders of magnitude.

He is the head of the Center of Embedded System-on-a-Chip Design funded by the New Jersey Commission on Science and Technology. The Center includes five faculty members from the Computer Engineering group at Princeton, and four others from Rutgers, NJIT, and Virginia Tech. It covers all aspects of SoC design, including analysis, synthesis, verification, electrical modeling and testing.

He is a fellow of IEEE and ACM, has served as an Associate Editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, and is currently serving as an Associate Editor of IEEE Transactions on Computer-Aided Design, IEEE Transactions on VLSI Systems, and Journal of Electronic Testing: Theory and Applications (JETTA). He has also served as the Program Chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems and the 2004 International Conference on Embedded and Ubiquitous Computing. He is the recipient of the AT&T Foundation Award and the NEC Preceptorship Award for research excellence, NCR Award for teaching excellence, and Princeton University Graduate Mentoring Award. His publications include three co-authored books, titled Testing and Reliable Design of CMOS Circuits (Kluwer, 1990), High-Level Power Analysis and Optimization (Kluwer, 1998), and Testing of Digital Systems (Cambridge University Press, 2003), and authoring or coauthoring of more than 250 technical papers. Six of his papers have won the Best Paper Award at ICCD '93, FTCS '97, ICVLSID '98, DAC '99, PDCS '02 and ICVLSID '03. Another paper of his was selected for ``The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years.'' He has received 11 U.S. patents.